Back-gated OFET Substrate

Descrição detalhada : Substrate: 150 mm wafer according to semiconductor standard (used for bottom-gate)Layer structure: .  Gate: n-doped silicon (doping at wafer surface: n~3x1017/ cm3).  Gate oxide: 230 nm +/- 10 nm SiO2 (thermal oxidation).  Drain/source:none.  Protection: resist AR PC 5000/3.1 (soluble in AZ-Thinner or acetone).  Layout: bare oxide but diced.  Chip size: 15 x 15 mm2.  No. of chips: 60 per wafer
Armazenamento : +15°C to +25°C
Embalagem : 1X1PAK