Back-gated OFET Interdigitated Substrate

Descrição detalhada : Substrate: 150 mm wafer according to semiconductor standard (used for bottom-gate)Layer structure: .  Gate: n-doped silicon (doping at wafer surface: n~3x1017/ cm3).  Gate oxide: 90 nm +/- 10 nm SiO2 (thermal oxidation).  Drain/source: 30 nm Au with 10 nm high work function adhesion layer (ITO), by lift-off technique.  Protection: resist AR PC 5000/3.1 (soluble in AZ-Thinner or acetone).  Layout: see images.  Test chip size: 15 x 15 mm2 .  No. of chips: 60 per wafer. Contact pads: 0.5 x 0.5 mm2 .  No. of transistors: 16 per wafer 4 x transistors L= 2.5 mum W= 10 mm 4 x transistors L= 5 mum W= 10 mm 4 x transistors L= 10 mum W= 10 mm 4 x transistors L= 20 mum W= 10 mm
Armazenamento : 15-25C
Embalagem : 1X1PAK